1. Field of the Invention
The present invention is directed to integrated circuit chips or chip carriers, such as modules or boards, containing X-Y wiring planes, and more particularly to a wiring arrangement for such carriers including orthogonal lines in the wiring pair for noise suppression.
2. Description of Related Art
U.S. Pat. No. 4,583,111 issued Apr. 15, 1986 to Early, entitled INTEGRATED CIRCUIT CHIP WIRING ARRANGEMENT PROVIDING REDUCED CIRCUIT INDUCTANCE AND CONTROLLED VOLTAGE GRADIENTS, discloses an integrated circuit chip wiring arrangement which provides reduced circuit inductance and controlled voltage gradients. Bonding pads are connected to logic gates which are physically adjacent to one another and power and ground busses are adjacent to one another relative to the logic gates.
More particularly, the area circumscribed by the current path on an integrated circuit chip is diminished, to thereby reduce the inductance of the chip and the likelihood of inductively generated errors, by disposing the bonding pads, through which the current source and current sink are respectively connected to logic gates, physically adjacent to one another. A further reduction in the area of the current loop is obtained by locating power and ground busses adjacent to one another relative to the logic gates. These two busses can be superposed one over the other on different metallic layers of the chip, so that the space between them is only the thickness of the isolation layer which separates the two metallic layers. The distribution of voltage to the logic gates is made uniform by varying the widths of the busses along their lengths in accordance with the currents they carry, and by ensuring that the total length of the current path for the gates is the same for every gate.
U.S. Pat. No. 3,904,886, issued Sept. 9, 1975 to Ehling et al, entitled VOLTAGE DISTRIBUTION SYSTEMS FOR INTEGRATED CIRCUITS, discloses a technique for damping unwanted noise by locating diffusion loops under voltage lines. More particularly, a technique is disclosed for damping unwanted power system oscillations present in an integrated circuit package. A very low d.c. impedance is achieved at any point in the voltage distribution system by a reduction in inductance, and increase in capacitance and an increase in a.c. resistance. The resistive voltage drop is achieved only at higher frequencies near the resonance frequency of the oscillations where it is needed. The scheme can be implemented on an integrated circuit chip by locating highly doped closed diffusion loops under the voltage supply lines or by placing metal layers on top of it. Further, a highly doped substrate has the same effect.
In U.S. Pat. No. 4,656,370, issued Apr. 7, 1987 to Kanuma entitled INTEGRATED CIRCUIT WITH DIVIDED POWER SUPPLY WIRING, an integrated circuit (IC) is provided with a plural set of power supply and ground lines within a package of the IC. Circuit elements, e.g., output buffers in the IC are divided into plural groups and each buffer group is coupled to the corresponding set of power supply and ground lines. Each set of the power supply and ground lines is provided with independent wirings so that the magnitude of current change in each wiring and the value of each wiring inductance become small.
U.S. Pat. No. 4,770,921, issued Sept. 13, 1988 to Wacker et al entitled SELF-SHIELDING MULTI-LAYER CIRCUIT BOARDS, discloses self-shielding multi-layer circuit boards which are produced utilizing augmentative replacement techniques.
Other wiring configurations are described in IBM Technical Disclosure Bulletin Publications, Vol. 28, No. 10, March 1986 at page 4618; Vol. 17, No. 5, October 1974 at page 135 and Vol. 27, No. 11, April 1985 at page 6578.